IMAGE ENCODER AND IMAGE PROCESSING SYSTEM

According to one embodiment, an image encoder configured to write coded image data in a memory includes an encoding module, a write address determining module, and a memory controller. The encoding module divides original image data including a plurality of pixels into a plurality of block lines, di...

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Bibliographic Details
Main Author UCHIYAMA MASATO
Format Patent
LanguageEnglish
Published 28.03.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
HANDLING RECORD CARRIERS
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
PRESENTATION OF DATA
RECOGNITION OF DATA
RECORD CARRIERS
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Summary:According to one embodiment, an image encoder configured to write coded image data in a memory includes an encoding module, a write address determining module, and a memory controller. The encoding module divides original image data including a plurality of pixels into a plurality of block lines, divides each block line into a plurality of sub-block lines, encodes the original image data in each sub-block line, and generates a plurality of coded sub-block lines. The write address determining module determines a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate. The memory controller writes the coded sub-block line in the write address corresponding to the coded sub-block line.
Bibliography:Application Number: US201113337934