METHOD TO ENABLE COMPRESSIVELY STRAINED PFET CHANNEL IN A FINFET STRUCTURE BY IMPLANT AND THERMAL DIFFUSION

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the...

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Main Authors MAITRA KINGSUK, MEHTA SANJAY C, ZHU ZHENGMAO, BERLINER NATHANIEL C, LOUBET NICOLAS, KULKARNI PRANITA, RONSHEIM PAUL A, YAMAMOTO TOYOJI
Format Patent
LanguageEnglish
Published 28.02.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
Bibliography:Application Number: US201113221198