COMBINED PLANAR FET AND FIN-FET DEVICES AND METHODS

Electronic devices (20, 20′) of superior design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS) (22) are obtained by providing multiple FIN-FETs (22) and at least one planar FET (32, 32′) on a common substrate (21), w...

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Bibliographic Details
Main Authors MAITRA KINGSUK, WAHL JEREMY A
Format Patent
LanguageEnglish
Published 28.02.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Electronic devices (20, 20′) of superior design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS) (22) are obtained by providing multiple FIN-FETs (22) and at least one planar FET (32, 32′) on a common substrate (21), wherein the multiple FIN-FETs (22) have fins (231, 232) of at least fin heights H1 and H2, with H2<H1. The multiple FIN-FETs (22) and the at least one planar FET (32, 32′) are separated vertically as well as laterally, which aids electrical isolation therebetween. Such electrical isolation can be enhanced by forming the planar FET (32) in a semiconductor region (441) insulated from the common substrate (21). In a preferred embodiment, the multiple height fins (231, 232) are obtained by first forming all fins (231, 232′) of common height H1 and then shortening some of the fins (232) to height H2<H1 by differentially etching upper portions thereof that have, preferably, been implanted with etch rate altering ions.
Bibliography:Application Number: US201113217061