METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral...

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Main Authors KIM KYUNGHYUN, LIM JONGHEUN, YOON BYOUNGMOON, PYO MYUNGJUNG, KIM HYO-JUNG, HAN JAHYUNG
Format Patent
LanguageEnglish
Published 17.01.2013
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Summary:According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.
Bibliography:Application Number: US201213545535