MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT

A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core...

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Bibliographic Details
Main Author SIKDAR DIPAK K
Format Patent
LanguageEnglish
Published 03.01.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal.
Bibliography:Application Number: US201213609172