PLL CIRCUIT

A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as...

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Bibliographic Details
Main Authors YAMADA YUJI, SOGAWA KAZUAKI, KINOSHITA MASAYOSHI
Format Patent
LanguageEnglish
Published 15.11.2012
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Summary:A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as a digital value; a selector configured to select either the digital value or a fixed value; a digitally controlled oscillator configured to oscillate at a frequency corresponding to the value selected by the selector; and a control section configured to instruct the selector to select the fixed value until receiving a start signal, and after receiving the start signal, instruct the selector to select the digital value, and the frequency division section to start output, at timing of an edge of the reference clock signal.
Bibliography:Application Number: US201213555674