Methods and Apparatus for Memory Word Line Driver

A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively...

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Bibliographic Details
Main Authors LIN JIHI-YU, YANG CHEN-LIN, CHAN WEI MIN, CHOU SHAO-YU, WANG LI-WEN
Format Patent
LanguageEnglish
Published 20.09.2012
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
Bibliography:Application Number: US201113051681