DETERMINING INTRA-DIE WIREBOND PAD PLACEMENT LOCATIONS IN INTEGRATED CIRCUIT

Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (I...

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Bibliographic Details
Main Authors CHUNG-MALONEY WAI LING, GRAF RICHARD S, ITOH HARUO
Format Patent
LanguageEnglish
Published 23.08.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.
Bibliography:Application Number: US201113032059