CLOCK DOMAIN CROSSING BUFFER

Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or...

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Bibliographic Details
Main Authors OSBORN MICHAEL J, TRESIDDER MICHAEL J, KOMMRUSCH STEVEN J, PARAKH PRIYANK, GRENAT AARON J, KIDD JOSEPH
Format Patent
LanguageEnglish
Published 03.05.2012
Subjects
ANALOGUE COMPUTERS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
Bibliography:Application Number: US20100938125