Method and Apparatus for Reducing Read Disturb in Memory

Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The re...

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Bibliographic Details
Main Authors LIU TSENG-YI, HUNG CHUN HSIUNG, HUNG SHUO-NAN
Format Patent
LanguageEnglish
Published 15.03.2012
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.
Bibliography:Application Number: US20100878299