METHOD AND SYSTEM OF HANDLING NON-ALIGNED MEMORY ACCESSES

A method and system to facilitate full throughput operation of cache memory line split accesses in a device. By facilitating full throughput operation of cache memory line split accesses in the device, the device minimizes the performance and throughput loss associated with the handling of non-align...

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Bibliographic Details
Main Author SHEAFFER GAD S
Format Patent
LanguageEnglish
Published 23.02.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method and system to facilitate full throughput operation of cache memory line split accesses in a device. By facilitating full throughput operation of cache memory line split accesses in the device, the device minimizes the performance and throughput loss associated with the handling of non-aligned cache memory accesses that cross two or more cache memory lines and/or page memory boundaries in one embodiment of the invention. When the device receives a non-aligned cache memory access request, the merge logic combines or merges the incoming data of a particular cache memory line from a data cache memory with the stored data of the preceding cache memory line of the particular cache memory line.
Bibliography:Application Number: US20100857933