SYNCHRONOUS LOGIC SYSTEM SECURED AGAINST SIDE-CHANNEL ATTACK

An improvement in the security of a logic system from attacks that observable features such as the power supply or electromagnetic radiation, so called, "side-channel attacks". Specifically, the present invention comprises a technique and method for reducing ability to monitor the relation...

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Bibliographic Details
Main Authors COYNE DAVID, DEAS ALEXANDER ROGER
Format Patent
LanguageEnglish
Published 27.10.2011
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:An improvement in the security of a logic system from attacks that observable features such as the power supply or electromagnetic radiation, so called, "side-channel attacks". Specifically, the present invention comprises a technique and method for reducing ability to monitor the relationship between currents in the system and the data in the system by closing the overall clock eye diagram, whilst keeping the eye diagram for connected stages open. The degree of eye closure for connected pipeline stages allows the system to run closer to its maximum operating speed compared to the use of system wide clock jitter, yet the overall closure provides security that is absent from systems with a partially open eye.
Bibliography:Application Number: US201113094022