METHOD AND APPARATUS FOR ANALYZING FAULT BEHAVIOR

An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior incl...

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Bibliographic Details
Main Authors PARK SACHOUN, LEE JUNG HEE
Format Patent
LanguageEnglish
Published 06.10.2011
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior includes an SMT processing block for performing a SMT processing using respective logic formulas corresponding to the protocol state machine diagram and the sequence diagram and outputted from the SMT conversion block, and determining whether the result of the SMT processing is satisfied to output an occurrable behavior scenario when the result of the SMT processing is satisfied.
Bibliography:Application Number: US20100912429