MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

• Main Authors: CHIU GEORGE L, WAIT CHARLES D, ASAAD SAMEH, EICHENBERGER ALEXANDRE E, OHMACHT MARTIN, BELLOFATTO RALPH E, RATTERMAN JOSEPH D, O'BRIEN JOHN K, CHER CHEN-YONG, BOYLE PETER, MARCELLA JAMES A, COTEUS PAUL W, HEIDELBERGER PHILIP, ELLAVSKY MATTHEW R, VAN OOSTEN JAMES L, BLOCKSOME MICHAEL A, DOZSA GABOR J, MUFF ADAM J, KNUDSON BRANT L, TAKKEN TODD E, MUNDY MICHAEL B, SUGAVANAM KRISHNAN, EISLEY NOEL A, TRAGER BARRY M, BLUMRICH MATTHIAS A, GUNNELS JOHN A, MAMIDALA AMITH R, O'BRIEN KATHRYN M, BRUNHEROTO JOSE R, STEINMACHER-BUROW BURKHARD, WU PENG, SMITH BRIAN, GARA ALAN, CHEN DONG, KOPCSAY GERARD V, EVANS KAHN C, STOCKDELL WILLIAM M, SATTERFIELD DAVID L, DAVIS KRISTAN D, STUNKEL CRAIG B, POOLE RUTH J, GOODING THOMAS M, SENGER ROBERT M, GIAMPAPA MARK E, HARING RUDOLF A, INGLETT TODD A, WATSON ALFRED T, GSCHWIND MICHAEL K, FLEISCHER BRUCE M, MILLER DOUGLAS R, CHRIST NORMAN, PARKER JEFFREY J, SUGAWARA YUTAKA, MILLER SAMUEL J, WISNIEWSKI ROBERT W, SALAPURA VALENTINA, WALKUP ROBERT E, KUMAR SAMEER, HALL SHAWN A, FOX THOMAS W, MEGERIAN MARK G
• Format: Patent
• Language: English
• Published: 08.09.2011
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.