Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy

A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal...

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Bibliographic Details
Main Authors RAMADURAI VINOD, PILO HAROLD
Format Patent
LanguageEnglish
Published 07.07.2011
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when column steering redundancy is requested. A plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in an array of memory cells. A second decoder receives the input address and selectively activates a first set of sense amplifiers of the plurality of sense amplifiers and selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated.
Bibliography:Application Number: US20100652345