VIA FORMING METHOD AND METHOD OF MANUFACTURING MULTI-CHIP PACKAGE USING THE SAME

A via forming method is provided. The via forming method includes: forming via-holes in a substrate; putting the substrate having the via-holes in a first solution to fill the via-holes with the first solution; sinking the metal particles into the via-holes by supplying a second solution containing...

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Bibliographic Details
Main Authors DO LEE MI, BAEK KYU HA, KIM DONG PYO, PARK KUN SIK
Format Patent
LanguageEnglish
Published 28.04.2011
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A via forming method is provided. The via forming method includes: forming via-holes in a substrate; putting the substrate having the via-holes in a first solution to fill the via-holes with the first solution; sinking the metal particles into the via-holes by supplying a second solution containing metal particles to the first solution, in which there is the substrate; and performing a first curing process of heat-treating the substrate having the via-holes filled with the metal particles so as to form vias in the via-holes. Further, a method of manufacturing a multi-chip package using the via forming method is provided.
Bibliography:Application Number: US20100835289