APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT

A plurality of tester channels is provided. The tester channels are capable of outputting double speed test patterns when a pin-multiplex-mode is designated. Each of the tester channels is provided with a level determination unit to output a level determination signal, a signal multiplexing unit, an...

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Bibliographic Details
Main Author KODASHIRO YOSHIAKI
Format Patent
LanguageEnglish
Published 09.12.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A plurality of tester channels is provided. The tester channels are capable of outputting double speed test patterns when a pin-multiplex-mode is designated. Each of the tester channels is provided with a level determination unit to output a level determination signal, a signal multiplexing unit, and an expected value comparison unit to receive an output from the signal multiplexing unit. The signal multiplexing unit multiplexes an outputted level determination signal obtained in one of the tester channels and a level determination signal obtained from a level determination unit of another one of the tester channels when a double speed test mode is designated. The signal multiplexing unit outputs a signal corresponding to the level determination signal of the one of the tester channels when the double speed test mode is canceled. A strobe time can be set individually for each of the tester channels to obtain a comparison result.
Bibliography:Application Number: US20100794183