Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits

• Main Authors: ASSADERAGHI FARIBORZ, SHEN JIE, CHUN JUNG-HOON, CHANG KUN-YUNG, PEREGO RICHARD E, LEE HAEANG
• Format: Patent
• Language: English
• Published: 04.11.2010
• Subjects: ANALOGUE COMPUTERS; AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; PHYSICS; RESONATORS

A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.