BASE STRUCTURE FOR III-V SEMICONDUCTOR DEVICES ON GROUP IV SUBSTRATES AND METHOD OF FABRICATION THEREOF

• Main Authors: KLEIMAN RAFAEL NATHAN, CHEONG DAN DAEWEON, PETER MANUELA, KOMARNYCKY NICHOLAS, PRESTON JOHN STEWART, ROBINSON BRADLEY JOSEPH
• Format: Patent
• Language: English
• Published: 21.10.2010
• Subjects: AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUSPOLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR; BASIC ELECTRIC ELEMENTS; CHEMISTRY; CRYSTAL GROWTH; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; METALLURGY; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; REFINING BY ZONE-MELTING OF MATERIAL; SEMICONDUCTOR DEVICES; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; SINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL ORUNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL

The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.