EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES

An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks...

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Main Authors IVANOVIC LAV D, GRINCHUK MIKHAIL, BOLOTOV ANATOLI, ZOLOTYKH ANDREJ A, GALATENKO ALEXEI V
Format Patent
LanguageEnglish
Published 08.04.2010
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
Bibliography:Application Number: US20080246812