DRAM HAVING STACKED CAPACITORS OF DIFFERENT CAPACITANCES

A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors h...

Full description

Saved in:
Bibliographic Details
Main Authors KIM JONG-SOO, WOO DONG-SOO
Format Patent
LanguageEnglish
Published 01.04.2010
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
TRANSMISSION
Online AccessGet full text

Cover

More Information
Summary:A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.
Bibliography:Application Number: US20090416722