METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING

A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to...

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Bibliographic Details
Main Authors GEMMEKE TOBIAS, MAEDING NICOLAS, PREISS JOCHEN
Format Patent
LanguageEnglish
Published 04.03.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
Bibliography:Application Number: US20080028889