FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT

A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduc...

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Bibliographic Details
Main Authors MELIK-MARTIROSIAN ASHOT, RUNNION ED, RANDOLPH MARK, DING MENG
Format Patent
LanguageEnglish
Published 04.02.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
Bibliography:Application Number: US20090557721