SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES

• Main Authors: SAFRANEK ROBERT J, BEERS ROBERT H, CHOU CHING-TSUN
• Format: Patent
• Language: English
• Published: 07.01.2010
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase.