PATTERNING METHOD AND SEMICONDUCTOR DEVICE

A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing,...

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Bibliographic Details
Main Authors IGETA MITSUAKI, TAKASE RIKIO, USUJIMA AKIHIRO, SUEDA MASAHIRO
Format Patent
LanguageEnglish
Published 24.12.2009
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Summary:A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
Bibliography:Application Number: US20090407158