MEMORY HAVING P-TYPE SPLIT GATE MEMORY CELLS AND METHOD OF OPERATION

A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocry...

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Bibliographic Details
Main Authors KANG SUNG-TAEG, WINSTEAD BRIAN A, HONG CHEONG M
Format Patent
LanguageEnglish
Published 03.12.2009
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.
Bibliography:Application Number: US20080130197