SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS

A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includ...

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Bibliographic Details
Main Authors BUTLER KENNETH M, SAXENA JAYASHREE, CARULLI, JR. JOHN M, VASAVADA AMIT P
Format Patent
LanguageEnglish
Published 20.08.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.
Bibliography:Application Number: US20080032557