Method of manufacturing a MOS transistor

A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed throug...

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Main Authors WU CHIHIANG, HUANG CHENG-TUNG, TU SHIH-JUNG, TING SHYH-FANN, JENG LI-SHIAN, CHENG YAOIN, HUNG WEN-HAN, SHIH CHUNG-MIN, TSENG CHI-SHENG, HSU SHIHIEH, LIN YU-MING, WU MENG-YI, LEE KUN-HSIEN, CHENG TZYY-MING
Format Patent
LanguageEnglish
Published 23.07.2009
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.
Bibliography:Application Number: US20080017065