METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA

A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the proc...

Full description

Saved in:
Bibliographic Details
Main Authors CAVIN ROBERT D, CARMEAN DOUGLAS M, ROHILLAH ANWAR, SPRANGLE ERIC
Format Patent
LanguageEnglish
Published 02.07.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
Bibliography:Application Number: US20070964631