Semiconductor memory system and wear-leveling method thereof

Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and alloca...

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Bibliographic Details
Main Authors CHO JUN-YOUNG, KIM SOO-JEONG, MOON MIN-SOO
Format Patent
LanguageEnglish
Published 18.06.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type. The semiconductor memory system is improved in performance and lifetime by managing wearing degrees over the logic block or the entries in accordance with the data type.
Bibliography:Application Number: US20080316508