Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits

In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground...

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Bibliographic Details
Main Authors PEDRAM MASSOUD, FALLAH FARZAN, PAKBAZNIA EHSAN
Format Patent
LanguageEnglish
Published 11.06.2009
Subjects
BASIC ELECTRONIC CIRCUITRY
CONTROLLING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Summary:In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa.
Bibliography:Application Number: US20080263341