STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS

A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to ea...

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Bibliographic Details
Main Authors HUNTER HILLERY C, HOULE ROBERT M, SANDON PETER A, BARTH, JR. JOHN E, HEDBERG ERIK L
Format Patent
LanguageEnglish
Published 04.06.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.
Bibliography:Application Number: US20080116234