Fixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions

• Main Authors: ESCOBAR VALDERRAMA GERARDO, MARTINEZ MONTEJANO MISAEL FRANSISCO, TORRES OLGUIN RAYMUNDO ENRIQUE
• Format: Patent
• Language: English
• Published: 23.04.2009
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

The present invention is an algorithm to implement a phase-locked loop (PLL) which is able to provide an estimation of the angular frequency, and both the positive and negative sequences of the fundamental component of a three-phase signal. These sequences are provided in fixed reference frame coordinates, and thus the proposed algorithm is referred as fixed reference frame PLL (FRF-PLL). In fact, the FRF-PLL does not require transformation of variables into the synchronous reference frame coordinates as in most PLL schemes. The detection of the positive sequence component of the source voltage at fundamental frequency is essential for the control and synchronization of systems coupled with the electric network, which are required to run even under grid disturbances such as unbalanced voltages, voltages sags, harmonic distortion and angular frequency variations. The design of the FRF-PLL is based on a complete description of the source voltage involving both positive and negative sequences in stationary coordinates and considering that the angular frequency is uncertain. Therefore the FRF-PLL is intended to perform properly under unbalanced conditions, and to be robust against angular frequency variations, providing a fast and precise response.