METHOD AND SYSTEM FOR GENERATING A LAYOUT FOR AN INTEGRATED ELECTRONIC CIRCUIT

A method to provide optimization between synthesis and layout in modern integrated circuit design, the method includes the steps of: a) identifying (210) a source (10) which has at least one associated sink (30) having a negative slack, i.e. the source having a negative slack at its output; b) findi...

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Bibliographic Details
Main Authors RINGE MATTHIAS, KOEHL JUERGEN
Format Patent
LanguageEnglish
Published 05.03.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method to provide optimization between synthesis and layout in modern integrated circuit design, the method includes the steps of: a) identifying (210) a source (10) which has at least one associated sink (30) having a negative slack, i.e. the source having a negative slack at its output; b) finding all sinks (30) driven by the identified source; and c) clustering (240) the sinks (30) according to timing and placement information read from a database, yielding a plurality of clusters (30a, 30b) of sinks, in which a cluster includes only a predetermined portion of the sinks.
Bibliography:Application Number: US20070942744