DATA PROCESSING SYSTEM AND METHOD FOR MONITORING THE CACHE COHERENCE OF PROCESSING UNITS

The present invention relates to a data processing system with a plurality of processing units (PU), a shared memory (M) for storing data from said processing units (PU) and an interconnect means (IM) for coupling the memory (M) and the plurality of processing units (PU). At least one of the process...

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Bibliographic Details
Main Authors MOORKANIKARA NAGESWARAN JAYRAM, TERECHKO ANDREI SERGEEVICH
Format Patent
LanguageEnglish
Published 05.03.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The present invention relates to a data processing system with a plurality of processing units (PU), a shared memory (M) for storing data from said processing units (PU) and an interconnect means (IM) for coupling the memory (M) and the plurality of processing units (PU). At least one of the processing units (PU) comprises a cache memory (C). Furthermore, a transition buffer (STB) is provided for buffering at least some of the state transitions of the cache memories (C) of said at least one of said plurality of processing units (PU). A monitoring means (MM) is provided for monitoring the cache coherence of the caches (C) of said plurality of processing units (PU) based on the data of the transition buffer (STB), in order to determine any cache coherence violations.
Bibliography:Application Number: US20050577592