MONITORING DEGRADATION OF CIRCIUT SPEED

A circuit, method, and computer readable medium that enables on-chip monitoring of transistor degradation. The circuit includes an on-chip reference ring oscillator electrically coupled to an on-chip reference counter. An on-chip stressed ring oscillator is electrically coupled to an on-chip test co...

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Bibliographic Details
Main Authors STAWIASZ KEVIN G, JENKINS KEITH A, BOLAM RONALD J
Format Patent
LanguageEnglish
Published 05.03.2009
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A circuit, method, and computer readable medium that enables on-chip monitoring of transistor degradation. The circuit includes an on-chip reference ring oscillator electrically coupled to an on-chip reference counter. An on-chip stressed ring oscillator is electrically coupled to an on-chip test counter. A test enable input is electrically coupled with the reference counter, the test counter, and the reference ring oscillator. When the test enable input is asserted the reference ring oscillator places a bit sequence proportional to the reference ring oscillator frequency on the reference counter simultaneously while the stressed ring oscillator places bit sequence proportional to the stressed ring oscillator frequency on the test counter. A difference in bit sequence between the reference counter and the test counter is compared to determine a relative difference there between.
Bibliography:Application Number: US20070847426