Silicon Tolerance Specification Using Shapes As Design Intent Markers

• Main Authors: LUGG ROBERT, MAYHEW JEFF, COTE MICHEL, RIEGER MICHAEL, HURAT PHILIPPE
• Format: Patent
• Language: English
• Published: 26.02.2009
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value 0) with a new layer, or alternatively using a conventional layer (e.g. metal 3) with a new datatype (e.g. value 1), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.