INTERNAL CLOCK DRIVER CIRCUIT

An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, th...

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Bibliographic Details
Main Author LEE KANG YOUL
Format Patent
LanguageEnglish
Published 11.12.2008
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
PHYSICS
PULSE TECHNIQUE
RESONATORS
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Summary:An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.
Bibliography:Application Number: US20070966225