Method and a Computer Readable Medium for Analyzing a Design of an Integrated Circuit
A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/co...
Saved in:
Main Authors | , , , |
---|---|
Format | Patent |
Language | English |
Published |
09.10.2008
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value. |
---|---|
Bibliography: | Application Number: US20080066225 |