CASCODE CURRENT MIRROR AND METHOD

A cascode amplifier (CA) ( 60 ) is described having a bottom transistor (T 1 new) with a relatively thin gate dielectric ( 67 ) and higher ratio (RB) of channel length (Lch 1 new) to width (W 1 new) and a series coupled top transistor (T 2 new) with a relatively thick gate dielectric ( 68 ) and a lo...

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Bibliographic Details
Main Authors YANG HONGNING, ZUO JIANG-KAI, PERKINS GEOFFREY W
Format Patent
LanguageEnglish
Published 18.09.2008
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Summary:A cascode amplifier (CA) ( 60 ) is described having a bottom transistor (T 1 new) with a relatively thin gate dielectric ( 67 ) and higher ratio (RB) of channel length (Lch 1 new) to width (W 1 new) and a series coupled top transistor (T 2 new) with a relatively thick gate dielectric ( 68 ) and a lower ratio (RT) of channel length (Lch 2 new) to width (W 2 new). An improved cascode current mirror (CCM) ( 74 ) is formed using a coupled pair of CAs ( 60, 60 '), one ( 60 ) forming the reference current (RC) side ( 601 ) and the other ( 60 ') forming the mirror current side ( 602 ) of the CCM ( 74 ). The gates ( 65, 65 ') of the bottom transistors (T 1 new, T 3 new) are tied together and to the common node ( 21 ) between the series coupled bottom (T 1 new) and top (T 2 new) transistors of the RC side ( 601 ), and the gates ( 66', 66 ') of the top transistors (T 2 new, T 4 new) are coupled together and to the top drain node ( 64 ) of the RC side ( 601 ). The area of the CCM ( 74 ) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
Bibliography:Application Number: US20070686439