Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods

A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are...

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Bibliographic Details
Main Authors JIN YOU-SEUNG, BAE CHOEL-HWYI
Format Patent
LanguageEnglish
Published 18.09.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided.
Bibliography:Application Number: US20080046065