SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT
A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
11.09.2008
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals. |
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| AbstractList | A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals. |
| Author | SATOI TOMOKI NISHIGAKI NAOHIKO |
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| Notes | Application Number: US20080042783 |
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| Snippet | A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable... |
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| SubjectTerms | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| Title | SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT |
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