SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT

A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay...

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Bibliographic Details
Main Authors SATOI TOMOKI, NISHIGAKI NAOHIKO
Format Patent
LanguageEnglish
Published 11.09.2008
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals.
Bibliography:Application Number: US20080042783