ENCAPSULATED CHIP SCALE PACKAGE HAVING FLIP-CHIP ON LEAD FRAME STRUCTURE AND METHOD

In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP o...

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Bibliographic Details
Main Authors FAUTY JOSEPH K, THIENPONT DENISE, LETTERMAN JAMES P
Format Patent
LanguageEnglish
Published 21.08.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
Bibliography:Application Number: US20080107568