Method and Apparatus for Enabling Resource Allocation Identification at the Instruction Level in a Processor System

An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor...

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Bibliographic Details
Main Authors SPANDIKOW CHRISTOPHER JOHN, MEIL GAVIN BALFOUR, ROBERT LEONARD
Format Patent
LanguageEnglish
Published 07.08.2008
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor hardware unit initiating a system bus request with a specific resource allocation group. The resource allocation group assigns a specific bandwidth allocation rate to the initiating processor. When a load, store, or I/O interface bus request reaches the I/O bus for execution, the resource allocation manager restricts the amount of bandwidth associated with each I/O request by assigning discrete amounts of bandwidth to each successive I/O requester. Successive stages of the instruction pipeline in the hardware unit contain the resource allocation identifiers (RAID) linked to the specific load, store, or I/O instruction.
Bibliography:Application Number: US20070671508