System-in-package (SiP) and method of manufacturing the same

Provided is a system-in-package (SiP) including a main chip and one or more sub chips. In the SiP, a first surface of the main chip is electrically connected with a second surface of the main chip, through a via electrode, the one or more sub chips are assembled on the second surface of the main chi...

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Bibliographic Details
Main Authors LEE HO-JIN, PARK MYEONG-SOON, LEE IN-YOUNG, SEO MOON-SUN
Format Patent
LanguageEnglish
Published 05.06.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Provided is a system-in-package (SiP) including a main chip and one or more sub chips. In the SiP, a first surface of the main chip is electrically connected with a second surface of the main chip, through a via electrode, the one or more sub chips are assembled on the second surface of the main chip on which a ReDistribution Line (RDL) is formed, and the length of the SiP is substantially equal to the length of the main chip.
Bibliography:Application Number: US20070895187