MEMORY WRAP TEST MODE USING FUNCTIONAL READ/WRITE BUFFERS

A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the proce...

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Bibliographic Details
Main Authors BRITTAIN MARK A, HOLLAWAY JOHN T, CORDERO EDGAR R, RETTER ERIC E
Format Patent
LanguageEnglish
Published 29.05.2008
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
Bibliography:Application Number: US20060466111