METHOD FOR OPTIMIZING PROBE CARD DESIGN
A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit (IC) die at semiconductor wafer test, while minimizing the number of times the probe card must be moved (number of "touchdowns")...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
27.12.2007
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!