METHOD FOR OPTIMIZING PROBE CARD DESIGN

A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit (IC) die at semiconductor wafer test, while minimizing the number of times the probe card must be moved (number of "touchdowns")...

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Bibliographic Details
Main Authors ALLEN MICHAEL R, GORE BROOKLIN J
Format Patent
LanguageEnglish
Published 27.12.2007
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit (IC) die at semiconductor wafer test, while minimizing the number of times the probe card must be moved (number of "touchdowns") to test all the IC die on a semiconductor wafer, as well as minimizing the number of individual IC die on the wafer that are probed more than once during the wafer test. Each specific arrangement of probe sites is tested against other patterns for efficiency in testing in what is known as a genetic algorithm. The most efficient patterns are moved into the next generation with modified features obtained by crossovers between two efficient individuals, and with random mutations, until a selected efficiency is obtained, or until a maximum number of generations have occurred.
Bibliography:Application Number: US20060420104