LAYOUT MAKING EQUIPMENT OF SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF MAKING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROCESS OF MANUFACTURE OF SEMICONDUCTOR DEVICE

• Main Author: ARIZONO TAKAMICHI
• Format: Patent
• Language: English
• Published: 06.12.2007
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The layout making equipment of a semiconductor integrated circuit is provided with a logic circuit schematic design section that design a logic circuit diagram, based on a specification data on a circuit, a layout data creation section that creates a layout data, based on the logic circuit diagram, a logic connection verification section that verifies whether or not a data on potentials inputted in nodes of the devices and nodes of connections between the devices extracted from the layout data match a data on the logic circuit diagram, thereby to create the results, a layout data verification section that verifies whether or not the layout data violates a design rule extracted from the specification data on the circuit, based on the data on the potentials inputted in the nodes of the devices and the nodes of the connections between the devices extracted in the logic connection verification section, thereby to create the verification results, and a data output section that outputs the created layout data.